original Core Huazhang proposed the design and scheme of edge system verification logic system, and the core Huazhang team

1 year ago (2024-01-25) Chief Editor
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Original title: Xin Huazhang Proposes the Design and Scheme of Edge System Verification Logic System

[Aiji Microreview] The design and scheme of logical system verification in the edge system proposed by Xin Huazhang connects the computing container image and hardware simulation tools through the resource mapper, and uses the computing container image and hardware simulation tools to perform verification tasks. This enables the management of cascaded hardware simulation tools or devices, and can continue to perform verification tasks in case of network problems, greatly improving the user experience.

In the electronic industry, EDA plays an increasingly important role due to the growing scale of the semiconductor industry, and most of the manufacturers using this technology are contract manufacturers engaged in semiconductor device manufacturing.

At present, the EDA industry usually uses the elastic computing power of the cloud platform, so there are many cloud applications through HPC. In addition, in the process of chip design, prototype verification is usually used to ensure the reliability and stability of functional modules.

However, the current combination of prototype verification and cloud platform has the following problems: for the prototype verification in the EDA industry, you need to use your own FPGA device, but each company's corresponding FPGA device is different, and each company has its own corresponding topology connection design.

Because the current cloud platform data is compatible with various hardware products, it is difficult to consider various situations of various companies' equipment. For example, GPU and FPGA devices are inserted into the server or physical machine and not connected to the platform through the network. Usually, the cloud platform is connected to the server or physical machine, so the current cloud platform does not consider the cascading of devices, and cannot manage the cascading hardware simulation tools or devices.

In view of the defects in the existing technology, Xin Huazhang applied for an invention patent entitled "Method of verifying logic system design in the edge system, edge system" (application number: 202210391096.3) on April 14, 2022. The applicant is Xin Huazhang Technology Co., Ltd.

According to the relevant information currently disclosed by the patent, let's take a look at this technical solution.

As shown in the above figure, it is the schematic diagram of the cloud computing system disclosed in the patent, which mainly includes the cloud server 120 and the edge system 130. The ECS can receive verification tasks designed by the logical system from the user host, and send verification tasks to the edge system. The edge system is composed of the edge host 134 and the hardware simulation tool 134a, which are connected to each other to perform verification tasks, and provide the interface to connect to the ECS and the interface to connect to the hardware simulation tool.

As shown in the above figure, it is the architecture diagram of the ECS. The ECS includes a console 220 and a data storage system 240. The console is configured to provide an interactive interface for users to control the ECS. For example, the console can provide a command line console or a visual interface to the user, allowing the user to select the edge system for the verification task, determine the description information of the logical system design (such as design files, RTL files, etc.), and determine the computing container image corresponding to the verification task.

The image of the computing container includes, for example, the software, running environment, or parameter configuration required to run the verification task. The data storage system stores the description files and simulation data that users need to design the logical system. In addition, the console can also connect with the edge system through interface 2201, and send the description of the logical system design (such as source code) and the computing container image corresponding to the verification task to the edge system through the interface.

In some devices, the console also has a built-in analyzer 2202, which is configured to apply for the use right of the edge host to ensure that the edge system performing the verification task can meet the estimated resources required for the verification task (for example, the network traffic data, space data, CPU data, memory data, etc. occupied by the verification task).

As shown in the figure above, it is a schematic diagram of the circular flow of the scheme. The analyzer creates a queue to be executed, adds the verification task to the queue to be executed, and when any edge system meets the estimated resources of the verification task in the queue to be executed, sends the computing container image to the edge system that meets the estimated resources, so that the edge system can execute the verification task in the queue to be executed.

When the analyzer determines that there is no edge system that meets the estimated resources of the verification task, the analyzer can create a queue to be executed and add the verification task that cannot be executed to the queue to be executed.

Finally, let's take a look at the overall verification journey diagram, as shown in the above figure. First, the analyzer determines the estimated resources required by the edge system to perform the verification task, whether the edge system meets the estimated resources, and whether the response edge system meets the estimated resources. If these conditions are met, the distributor sends the computing container image to the edge system, and then performs the verification task.

If the analyzer determines that the edge system connected to the ECS does not meet the estimated resources, which may include the network traffic data, spatial data, CPU data, etc. occupied by the edge system when executing the verification task, the analyzer will add the verification task to the queue to be executed to execute the above circular process.

The above is the logic system design and scheme proposed by Xin Huazhang to verify on the edge system. This scheme connects the computing container image and hardware simulation tools through a resource mapper, and uses the computing container image and hardware simulation tools to perform verification tasks. This enables the management of cascaded hardware simulation tools or devices, and can continue to perform verification tasks in case of network problems, greatly improving the user experience. Go back to Sohu to see more

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This article is written by: Chief Editor Published on Software Development of Little Turkey , please indicate the source for reprinting: //hongchengtech.cn/blog/4422.html
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